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Keynote & Invited Speakers


Keynote: Power Management in UTBB FD-SOI Circuits

Speaker: Diego Puschini
CEA-LETI, MINATEC, France

Abstract: 

UTBB FD-SOI technology offers new opportunities and challenges for circuit designers, promising extraordinary power saving and performance figures. This talk will present a power management technique taking advantage of the very wide Body Biasing range offered by this technology, combined with efficient Adaptive Voltage and Frequency Scaling techniques. The proposed approach makes use of intelligent power mode selection in order to efficiently increase the total power saving. Results have been measured on a 32-bit VLIW DSP with a Body Biasing Voltage scaling from 0V up to +/-2V combined with an AVFS mechanism in UTBB FD-SOI 28nm.

 

Invited talk 1: Synergistic Energy Harvesting from Radio Waves by Photovoltaic-Assisted CMOS Rectifier

Speaker: Koji KOTANI
Department of Electronics, Graduate School of Engineering, Tohoku University

Abstract:

Synergistic energy harvesting concept, where multiple environmental energy sources existing simultaneously are utilized in a cooperative manner, is proposed.  As one example realization of the concept, a photovoltaic (PV)-assisted CMOS rectifier is demonstrated in this paper. A p-n junction diode acting as a PV cell converts light energy to a dc bias voltage, which compensates the threshold voltage of the MOSFETs and enhances the RF to DC power conversion efficiency (PCE) of the rectifier especially under low input power conditions.  Based on the physics-based analyses of the PV cell operation, symmetric PV cell structures for balanced biasing and output-voltage-boost PV cell structures to further increase the bias voltages are proposed and improved efficiencies of the rectifiers are experimentally verified. Under typical indoor lighting conditions, a PCE greater than 25% was achieved at an RF input power, frequency, and output load of ?20 dBm, 920 MHz and 47 kOhm, respectively, which is more than three times the value obtained by a conventional rectifier without PV assistance.

 

Invited talk 2:  Advanced techniques for E-Fuse application

Tatsuru MATSUO
Fujitsu Laboratories Ltd.

Abstract:

Electrical fuse (E-Fuse) is a one-time programmable non-volatile memory that has been widely used in applications such as memory redundancy, chip ID, and so on. However, the write operation time and area of the E-Fuse become a problem when using large amounts of E-Fuses. This paper presents two advanced E-Fuse techniques. One is the E-Fuse circuit that can shorten the write operation time in memory redundancy application. The other technique enables to reduce the area in memory redundancy and chip ID application.

 

Invited talk 3:  Multi Patterning Techniques for Manufacturability Enhancement in Optical Lithography

Atsushi TAKAHASHI (Tokyo Institute of Technology), Ahmed AWAD (Tokyo Institute of Technology),
Yukihide KOHIRA (The University of Aizu), Tomomi MATSUI (Tokyo Institute of Technology),
Chikaaki KODAMA (Toshiba Corporation), Shigeki NOJIMA (Toshiba Corporation) and Satoshi TANAKA (Toshiba Corporation)

Abstract:

In this paper, various kinds of multiple patterning techniques such as double-patterning (DP) and triple-patterning (TP) which are being developed to fabricate small features onto wafer are introduced. In order to fabricate small features which are smaller than the wavelength of optics used in equipment of optical lithography, various kinds of manufacturing processes such as litho-etch litho-etch process (LELE), self-aligned (sidewall) process (SA), and cut process (CUT) are used to make a design and manufacturing flow robust in practice. In order to adapt to various kinds of situations, various kinds of design and manufacturing flows are being investigated. Each design and manufacturing flow has its own properties, and the design flexibility and reliability of pattern on wafer are different from each other. Recent results on design for manufacturability mainly obtained from us are introduced.

 

Invited talk 4: Perpetuum-Mobile Sensor Network Systems using a CPU on 65nm SOTB CMOS Technology

Koichiro Ishibashi1, Cong-Kha Pham1, Nobuyuki Sugii2 
1) The University of Electro-Communications, Tokyo, Japan;
2) Low-power Electronics Association & Project (LEAP), Tsukuba, Japan

Abstract:

This paper discusses a condition to attain energy harvesting sensor network systems, which can make the Trillion Sensor Universe into reality. Power consumption which is needed to realize each IoT application is also shown. We demonstrate a 32-bit CPU which operates with 13.4 pJ/cycle Emin as well as 0.14 μA sleep current, so that it meets the requirements of the power consumption for the energy harvesting sensor network systems. The CPU was fabricated using 65nm SOTB CMOS (Silicon On Thin Buried oxide) technology.

 

Invited talk 5: A/D Converter Trends and Topics in ISSCC 2014

Takahiro Miki, Renesas Electronics

Abstract:

Techniques and performances of A/D converters have been,,dramatically improved in these 7-8 years aiming for greener,,and smarter society. In the first half of this talk, recent trends in,,performance (speed, accuracy and energy efficiency) are analyzed.,,Some A/D conversion techniques highlighted in ISSCC 2014 are introduced,,in the second half.

 

Invited talk 6: Analog to Digital Converters for Mili-meter Wave Wireless Communications

Masaya Miyahara, Ibuki Mano, Masaaki Nakayama, Kenichi Okada, and Akira Matsuzawa, Tokyo Institute of Technology
 

Abstract

This paper presents analog to digital converters (ADCs) for mili-meter wave (mmW) wireless communications. A 2.2GS/s 7b time-based folding ADC with resistively averaged voltage-to-time amplifiers (V-T amps) has been developed for 60GHz receivers. This time-based folding architecture consists of simple logic cells with a folding factor of 8 instead of the conventional static amplifiers. Resistively averaged V-T amps have a low offset voltage and a high conversion gain to relax the offset requirement for the SR-latch. This ADC achieves an SNDR of 37.4dB at Nyquist frequency without any calibration technique.

 

Invited talk 7: Challenges beyond 2010s against Terrestrial Radiation-Induced Failures in Electronic Systems

Eishi Ibe, Tadanobu Toba, Ken-ichi Shimbo, and Takumi Uezono, Hitachi.

Abstract:

Threats to highly sophisticated nano-scale digital electronic systems caused by terrestrial radiations are being widely awared in a variety of industrial fields, such as aerospace, automobile, networks, and supercomputers.,,In the present talk, such growing threats are briefly reviewed and challenges necessary for breakthrough to substantiate RAS (Reliability, Availability and Serviceability) under the threats are highlighted.,,Important directions for such challenges, typically including non-stop operation of electronic systems and symptom-driven cross-layer recovery (SDCLR) strategies under falty system conditions are proposed.

 

Invited talk 8: A 56-Gb/s Receiver Front-End with a CTLE and 1-Tap DFE in 20-nm CMOS 

Yasufumi Sakai, Takayuki Shibasaki, Hisakatsu Yamaguchi, Toshihiko,Mori, Yoichi Koyanagi, and Hirotaka Tamura, Fujitsu Laboratories Ltd.

Abstract:

This paper shows a 56-Gb/s receiver front-end suited for baud-rate clock recovery.,Sharing the comparators for the data decision and phase detection minimizes the number of comparators in the front-end and reduces the power consumption.,The front-end has a continuous-time linear equalizer followed by a 1-tap speculative decision-feedback equalizer.,The front-end operates at 56Gb/s with a bit error rate of less than 10-12 with a 0.4UI margin in the bathtub curve.,It occupies 0.27mm2 and consumes 177mW of power from a 0.9-V supply. 


Invited talk 9: CMOS Platforms for Biomedical Application -- DNA Sequencing, Glucose Detection, and Bacteria Counting

Kiichi NIITSU, Kazuo NAKAZATO, Nagoya University, Japan

Abstract:

The paper introduces design and realization of CMOS platforms for biomedical application. Since CMOS electronics has high-integration, high-sensitivity, high-speed, and low-power capability, it is attracting for biomedical application and intensely developed. We have developed CMOS platforms with cost-effective 0.6-um CMOS technology for biomedical application. In this paper, CMOS platforms enabling DNA sequencing, Glucose detection, and bacteria counting are introduced.