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Keynote & Invited Speakers

TJMW-Special Talk

Seven Physical Meanings of the Quality Factor in Resonators and Oscillators

Takashi Ohira, Toyohashi University of Technology, Japan


Takashi Ohira received the B.E. and D.E. degrees in communication engineering from Osaka University, Osaka, Japan, in 1978 and 1983. In 1983,he joined NTT Electrical Communication Laboratories, Yokosuka, Japan, where he was engaged in research on monolithic integration of microwave semiconductor devices and circuits. He developed GaAs MMIC transponder modules and microwave beamforming networks aboard Japanese national multibeam communication satellites, Engineering Test Satellite VI (ETS-VI) and ETS-VIII, at NTT Wireless Systems Laboratories, Yokosuka, Japan.

Since 1999, he has been engaged in research on wireless ad-hoc networks and microwave analog adaptive antennas aboard consumer electronic devices at ATR Adaptive Communications Research Laboratories, Kyoto, Japan. Concurrently he was a Consulting Engineer for National Space Development Agency (NASDA) ETS-VIII Project in 1999, and an Invited Lecturer for Osaka University from 2000 to 2001. From 2005, he was Director of ATR Wave Engineering Laboratories, Kyoto, Japan. Currently, he is Professor of Toyohashi University of Technology. He coauthored Monolithic Microwave Integrated Circuits (Tokyo: IEICE, 1997). Prof. Ohira was awarded the 1986 IEICE Shinohara Prize, the 1998 APMC Prize, and the 2004 IEICE Electronics Society Prize. He serves as President of IEICE Microwave Technical Group. He is an IEEE Fellow, IEEE MTT-S Kansai Chapter Founder, and IEEE MTT-S Nagoya Chapter Founder.

Keynote Talk

Challenge for Normally-Off Computing

       Toru Shimizu, Yohei Sato, Hiroshi Ueki, Shintaro Mori, Hiroyuki Kawai, Masanori Hayashikoshi,Renesas, Japan

       Hiroshi Nakamura, University of Tokyo, Japan

Toru Shimizu was born in 1958.
He received Ph.D. degree in computer science from University of Tokyo in 1986.
Since then, he has been working for R&D of microprocessor and micro-controller architecture in Mitsubishi Electric and Renesas Corporations.
In 1997, he got the 1997 R&D 100 award by the development of world's 1st commercial microprocessor with on-chip DRAM called "M32R/D".
It triggered a lot of SoC designs integrating microprocessors and large embedded DRAMs in consumer and communication applications.
In 2004, he and his R&D group presented "A dual-CPU symmetric multi-processing microprocessor with a large shared on-chip memory" in the ISSCC 2004.
It showed broad application possibilities of the multi-core technology for embedded areas such as automotive applications.
From 2006 to 2011, he was in charge of R&D for microprocessor and micro-controller development platform as a general manager in Renesas.
He is now in charge of R&D collaboration with universities, academic societies, and government projects.
He is a senior member of the IEEE and the IEICE Japan.
He is also the Organizing Committee Chair of the Asian Solid-State Circuits Conference 2012 "A-SSCC 2012".
He will welcome your attendance at the A-SSCC in KOBE, JAPAN in November.

Challenge of 24bit-class Analog in Audio DAC

Toshihiko Hamasaki, Hiroshima Institute of Technology, Japan


Prof. Hamasaki received Ph.D degree form Graduate School of Science and Technology, Hiroshima University in 1984.
Since 1984, he had been working for VLSI Research Center, TOSHIBA Corp. His research topics were Silicon-on-Insulator 3-D LSI Technology and Bipolar Junction Transistor SPICE Modeling.
Since 1991, he had been working for Burr-Brown Incorporated as Design Manager in Audio and Imaging DAC/ADC.
Since 2001, he had been working for DCES Company, Texas Instruments Incorporated as Analog Technology Center Director.
In 2004, he received TI Fellow, and
In 2008 he became Analog Signal Chain Technology Office Manager.
Since 2010, he has been Professor of Hiroshima Institute of Technology
His Research Area is Audio Signal Processing and Ultra Low Power Sensor Network

Invited Talk

Power Integrity Design For Low Power Supply Voltage Applications

Yutaka Uematsu, Masayoshi Yagyu, and Hideki Osaka, Yokohama Research Lab., Hitachi, Ltd., Japan


Yutaka Uematsu received his Doctor of Philosophy of engineering in electrical and communication from Tohoku University in 2001, and joined Hitachi Ltd. Japan.

Now he is a senior researcher of Yokohama Research Laboratory of Hitachi. His area of expertise is signal and power integrity design for LSI, LSI package, and printed circuit board. He has been involved in the signal and power integrity design of memory such as DRAM, SRAM, and ASIC, and SerDes LSI.

Design of Low-loss on-chip passive devices in CMOS technology for 60 GHz band and Status of LSI Education in E-JUST, a Japanese-Style University in Egypt

Ramesh K. Pokharel, R. Dong, and K. Yoshida, Kyushu University, Japan


Ramesh K. Pokharel received the M. E. and Doctorate degrees from the University of Tokyo, Japan in 2000 and 2003, respectively all in electrical engineering. He had short academic and industrial experiences in Nepal before he joined the University of Tokyo in 1997 as a research student. He had been a post-doctoral research fellow with the Department of Electrical Engineering and Electronics, Aoyama Gakuin University, Japan from April 2003 to March 2005.

In April 2005, he joined the Department of Electronics, Graduate School of Information Science and Electrical Engineering, Kyushu University, and since September 2010, he has been a Professor at the Center for Japan-Egypt Cooperation in Science and Technology, Kyushu University. His current research interests include the low cost RFIC and analog circuits for microwave and millimeter wave wireless communications, on-chip signal integrity issues, and on-chip meta-materials in CMOS. He is a member of the IEEE. Dr. Pokharel was a recipient of the Monbu-Kagakusho Scholarship of the Japanese Government from 1997-2003, and an excellent COE research presentation award from the University of Tokyo in 2003. He has been serving as a secretory of IEEE MTT-S Japan Chapter since Jan. 2011 and as a vice-director of E-JUST center, Kyushu University, Japan since April, 2012.

Leader in Functional Verification Solution - Mentor Graphics

Derek Jao, Mentor Graphics, USA


Over 10 years FPGA/ASIC design and verification experience. Help customers in Taiwan, China, India and many other Asian countries to build up their FPGA/ASIC verification flow with Mentor solution. Master's degree of Computer Science and Information Engineering from National Chiao-Tung University in Taiwan.

Analog Front-End Design for CMOS High-Speed I/O

Masaya Kibune, Hirotaka Tamura, Fujitsu Laboratories Ltd., Japan


Masaya Kibune was born in Kanagawa, Japan, in 1973. He received the B.S. and M.S. degrees in Applied Physics from Tokyo University in 1996 and 1998 respectively.
In 1998, he joined Fujitsu Laboratories, Ltd., Kanagawa, Japan. He has been engaged in research and design of high-speed IO with CMOS. He is a TPC member in ASSCC from 2012.

Education and Learning

Ellen Tam, Cadence, USA


Ellen Tam is the Group Director of Strategic Programs and Initiatives at Cadence Design Systems, Inc. Over the last 25 years, Ms. Tam has held various positions in application engineering, customer hotline support, services, and business operations. Currently Ms. Tam is focused on strategic programs and initiatives for developing new education programs. She has experience in various areas such as customer-facing support, consulting services, organizational management, customer education, internal development and process, and infrastructure. She has also been involved in projects affecting global operations, especially in the emerging markets.

Before joining Cadence, Ms. Tam worked at the first semiconductor company in Hong Kong. She received her bachelor’s degree in Computer Science from the University of Ottawa.

Khoa Nguyen, AMD, USA


Khoa Nguyen is the Sr. Manager of CAD Design Engineering at AMD. His current responsibilities include defining methodology for post layout extraction and verification (Electrical Analysis) for high performance designs, interfacing with EDA partners and foundries. Prior to joining AMD, Khoa was the Vice President of Technical Marketing and Applications at Silicon Frontline, a leading provider of 3D parasitic extraction and analysis tools. Prior to Silicon Frontline, Khoa served as Director of Product Engineering for Extraction and Analysis Products at Cadence Design Systems. Prior to Cadence, Khoa served as Senior R&D Manager at Simplex Solutions developing Fire&Ice- a leading parasitic extraction product. Khoa was also the Vice President of Engineering at CAD Artisans developing AuSim- a Verilog compatible simulator. Khoa has more than 25-year experience in EDA and Semiconductor business. Khoa received his Bachelor Degree in Computer Engineering from University of California and Executive MBA from University of San Diego.

Task Assignment Methods for Multi-Processor System considering Dynamic Voltage Frequency Scaling

Yoshinori Takeuchi, Taichiro Shiraishi, Keishi Sakanushi, and Masaharu Imai, Osaka University, Japan


He received his B.E., M.E.and Dr. Eng. degrees from Tokyo Institute of Technology in 1987, 1989 and 1992, respectively. From 1992 through 1996, he was a research associate of Department of Engineering, Tokyo University of Agriculture and Technology. From 1996, he has been with the Osaka University. He was a visiting scholar in University of California, Irvine from 2006 to 2007. He is currently an Associate Professor of Graduate School of Information Science and Technology at Osaka University. His research interests include System Level Design, VLSI design and VLSI CAD. He is a member of IEICE of Japan, IPSJ, ACM, and SP, CAS and SSC Society of IEEE.